
#include "drv_dsp.h"

#ifdef SUPPORT_FM1505_DMS

// #PLATFORM_NAME  FM1505
// #SINGLE_API_VER  1.3.0
// #PARAM_MODE  Simple
// #CASE_NAME  New
// #PARAM_TYPE  TX+RX
// #TOTAL_CUSTOM_STEP  0
// #FM_ALG_PARAM_BASE_OFFSET  0x00
// #1mic fine-tuned on newEVM
    
//16K
const reg_config_t dsp_mode1_ven_TX[] =
    {
	{0	 ,0x0001},	  // 00,	OP_MODE_REG :  HF + VR mode； Bit1: 1：HF; 0: HS																														  
	{1	 ,0x0000},	  // 01,	OP_MODE_REG1:  CAR_mode 																														   
	{2	 ,0x0368},	//0x1B68	// 02,	  SEND_FUNC_REG: AEC+NS+EQ+Lout_HPF+DRC; bit11:MIC preEQ Bit12:initialEcho; bit10： NASSA on/off,0x0400																											  
	{3	 ,0x0000},	  // 03,	SEND_FUNC_MODE1,  no mapping																													   
	{4	 ,0x0001},	  // 04,	MIC_NUM 																																		   
	{5	 ,0x0001},	  // 05,	SYS_SAMPLINGFREQ_SIG,	 0:8k,	1:16k,	3:32k				   
	{6	 ,0x0001},	  // 06,	SYS_SAMPLINGFREQ_PROC,	no mapping																												   
	{7	 ,0x000A},	  // 07,	SYS_FRAME_SZ_SIG,  no mapping																													   
	{8	 ,0x000A},	  // 08,	SYS_FRAME_SZ,		subframe time duration in mili-second. Can only support set of [8K_10ms, 16K_10ms, 16K_8ms, 32k_5ms].				  
	{9	 ,0x0000},	  // 09,	SYS_DELAY_OPT																																	   
	{10  ,0x0040},	  // 0A,	SYS_MAX_TAIL_LENGTH 																															   
	{11  ,0x0001},	  // 0B,	NUM_LOUT_CHN,  no mapping																														   
	{12  ,0x0002},	  // 0C,	MAXNUM_AECREF,	Stereo/mono 																														
	{13  ,0x1000},	  // 0D,	DBG_FUNC_REG ; Bit12:SSA40 on/off																																	   
	{14  ,0x0000},	  // 0E,	SYS_RESERV_0																																	
	{15  ,0x0000},	  // 0F,	SYS_RESERV_1																																	
	{16  ,0x0000},	  // 10,	SYS_RESERV_2																																	
	{17  ,0x0000},	  // 11,	SYS_RESERV_3																																	
	{18  ,0x0000},	  // 12,	DIST2REF00: 	 0, 		 Q0 format in mm																									   
	{19  ,0x0055},	  // 13,	DIST2REF01:    Q0 format in mm	A18=0x55																										  
	{20  ,0x0064},	  // 14,	DIST2REF02:    no mapping																										   
	{21  ,0x00AA},	  // 15,	DIST2REF03:   no mapping																										  
	{22  ,0x0000},	  // 16,	DIST2REF04:    no mapping																																 
	{23  ,0x0000},	  // 17,	DIST2REF05:    no mapping																																  
	{24  ,0x0000},	  // 18,	MMIC_INDEX,  no mapping 																														   
	{25  ,0x0800},	  // 19,	MICPGA_GAIN0:  unit gain, [0,7FFF)																												   
	{26  ,0x0800},	  // 1A,	MICPGA_GAIN1:  unit gain, [0,7FFF)																												   
	{27  ,0x0800},	  // 1B,	MICPGA_GAIN2:  no mapping																												  
	{28  ,0x0800},	  // 1C,	MICPGA_GAIN3:  no mapping																												  
	{29  ,0x0800},	  // 1D,	MICPGA_GAIN4:  no mapping																												  
	{30  ,0x0800},	  // 1E,	MICPGA_GAIN5:  no mapping																												  
	{31  ,0x0001},	  // 1F,	MIC_MAX_PAIRS: no mapping																														   
	{32  ,0x0000},	  // 20,	MIC_PAIRS_HS,  no mapping																														   
	{33  ,0x0002},	  // 21,	MICS_FOR_BF,  no mapping																														   
	{34  ,0x0000},	  // 22,	MIC_PAIRS_FORL1,  no mapping																													   
	{35  ,0x0002},	  // 23,	MICS_OF_PAIR0	reserved																																   
	{36  ,0x0002},	  // 24,	MICS_OF_PAIR1	reserved																																   
	{37  ,0x0002},	  // 25,	MICS_OF_PAIR2	reserved																																   
	{38  ,0x0002},	  // 26,	MICS_OF_PAIR3	reserved																																   
	{39  ,0x0000},	  // 27,	MIC_PAIR_CH00	reserved																																   
	{40  ,0x0001},	  // 28,	MIC_PAIR_CH01	reserved																																   
	{41  ,0x0002},	  // 29,	MIC_PAIR_CH02	reserved																																   
	{42  ,0x0003},	  // 2A,	MIC_PAIR_CH03	reserved																																   
	{43  ,0x0000},	  // 2B,	MIC_PAIR_CH04,	Reserved																														   
	{44  ,0x0000},	  // 2C,	MIC_PAIR_CH05,	Reserved																														   
	{45  ,0x0000},	  // 2D,	MIC_PAIR_CH10	reserved																																   
	{46  ,0x0002},	  // 2E,	MIC_PAIR_CH11	reserved																																   
	{47  ,0x0000},	  // 2F,	MIC_PAIR_CH12	reserved																																   
	{48  ,0x0000},	  // 30,	MIC_PAIR_CH13	reserved																																   
	{49  ,0x0000},	  // 31,	MIC_PAIR_CH14,	Reserved																														   
	{50  ,0x0000},	  // 32,	MIC_PAIR_CH15,	Reserved																											  
	{51  ,0x0000},	  // 33,	MIC_PAIR_CH20	Reserved																													  
	{52  ,0x0003},	  // 34,	MIC_PAIR_CH21	Reserved																													  
	{53  ,0x0000},	  // 35,	MIC_PAIR_CH22	Reserved																													  
	{54  ,0x0000},	  // 36,	MIC_PAIR_CH23	Reserved																													  
	{55  ,0x0000},	  // 37,	MIC_PAIR_CH24,	Reserved																											  
	{56  ,0x0000},	  // 38,	MIC_PAIR_CH25,	Reserved																											  
	{57  ,0x0000},	  // 39,	MIC_PAIR_CH30	reserved																													 
	{58  ,0x0000},	  // 3A,	MIC_PAIR_CH31	reserved																													 
	{59  ,0x0000},	  // 3B,	MIC_PAIR_CH32	reserved																													 
	{60  ,0x0000},	  // 3C,	MIC_PAIR_CH33	reserved																													 
	{61  ,0x0000},	  // 3D,	MIC_PAIR_CH34,	Reserved																											  
	{62  ,0x0000},	  // 3E,	MIC_PAIR_CH35,	Reserved																											  
	{63  ,0x0001},	  // 3F,	MICFORBF_MARK0,  no mapping 																										  
	{64  ,0x0001},	  // 40,	MICFORBF_MARK1,  no mapping 																										  
	{65  ,0x0001},	  // 41,	MICFORBF_MARK2,  no mapping 																										  
	{66  ,0x0001},	  // 42,	MICFORBF_MARK3,  no mapping 																													   
	{67  ,0x0001},	  // 43,	MICFORBF_MARK4,  no mapping 																													   
	{68  ,0x0001},	  // 44,	MICFORBF_MARK5,  no mapping 																													   
	{69  ,0x0000},	  // 45,	DIST2REF10: 	 Reserved																													 
	{70  ,0x0028},	  // 46,	DIST2REF11: 	 Reserved																													  
	{71  ,0x0000},	  // 47,	DIST2REF12: 	 Reserved																													  
	{72  ,0x0000},	  // 48,	DIST2REF13: 	 Reserved																													  
	{73  ,0x0000},	  // 49,	DIST2REF14: 	 Reserved																													  
	{74  ,0x0000},	  // 4A,	DIST2REF15: 	 Reserved																													  
	{75  ,0x0000},	  // 4B,	DIST2REF20: 	 Reserved																													  
	{76  ,0x0051},	  // 4C,	DIST2REF21: 	 Reserved																													  
	{77  ,0x0000},	  // 4D,	DIST2REF22: 	 Reserved																													  
	{78  ,0x0000},	  // 4E,	DIST2REF23: 	 Reserved																													  
	{79  ,0x0000},	  // 4F,	DIST2REF24: 	 Reserved																													  
	{80  ,0x0000},	  // 50,	DIST2REF25: 	 Reserved																													  
	{81  ,0x0000},	  // 51,	DIST2REF30: 	 Reserved																													  
	{82  ,0x0000},	  // 52,	DIST2REF31: 	 Reserved																													  
	{83  ,0x0000},	  // 53,	DIST2REF32: 	 Reserved																													  
	{84  ,0x0000},	  // 54,	DIST2REF33: 	 Reserved																													  
	{85  ,0x0000},	  // 55,	DIST2REF34: 	 Reserved																													  
	{86  ,0x0000},	  // 56,	DIST2REF35: 	 Reserved																													  
	{87  ,0x0000},	  // 57,	MIC_LOC_00,  no mapping 																														
	{88  ,0x0000},	  // 58,	MIC_LOC_01,  no mapping 																														
	{89  ,0x0000},	  // 59,	MIC_LOC_02,  no mapping 																														
	{90  ,0x0000},	  // 5A,	MIC_LOC_03,  no mapping 																														
	{91  ,0x0000},	  // 5B,	MIC_LOC_04,  no mapping 																														
	{92  ,0x0000},	  // 5C,	MIC_LOC_05,  no mapping 																														
	{93  ,0x0000},	  // 5D,	MIC_LOC_20,  no mapping 																														
	{94  ,0x0000},	  // 5E,	MIC_LOC_21,  no mapping 																														
	{95  ,0x0000},	  // 5F,	MIC_LOC_22,  no mapping 																														
	{96  ,0x0000},	  // 60,	MIC_LOC_23,  no mapping 																										   
	{97  ,0x0000},	  // 61,	MIC_LOC_24,  no mapping 																										   
	{98  ,0x0000},	  // 62,	MIC_LOC_25,  no mapping 																										   
	{99  ,0x0000},	  // 63,	MIC_LOC_30,  no mapping 																										   
	{100 ,0x0000},	  // 64,	MIC_LOC_31,  no mapping 																										   
	{101 ,0x0000},	  // 65,	MIC_LOC_32,  no mapping 																										   
	{102 ,0x0000},	  // 66,	MIC_LOC_33,  no mapping 																										   
	{103 ,0x0000},	  // 67,	MIC_LOC_34,  no mapping 																										   
	{104 ,0x0000},	  // 68,	MIC_LOC_35,  no mapping 																										   
	{105 ,0x0000},	  // 69,	RULER_MODE,  no mapping 																										   
	{106 ,0x0020},	  // 6A,	AECREF_VAD_THRD
	{107 ,0x0002},	  // 6B,	INITIAL_REF_SIL_CNT
	{108 ,0x0000},	  // 6C,	initial_supp_rpt_times
	{109 ,0x0000},	//0x000A	// 6D,	  INITIAL_ECHO_SUPP_3DB_STEP
	{110 ,0x0000},	  // 6E,	Reserved
	{111 ,0x0028},	  // 6F,	INITIAL_ECHO_SUPP_CNT; frame
	{112 ,0x0000},	  // 70,	MIC_RESERV_6																													   
	{113 ,0x0400},	  // 71,	PID_NASSA_SMOOTH  //PATCH_CTRL_REG																														 
	{114 ,0x7B02},	  // 72,	A_HP																																 
	{115 ,0x4000},	  // 73,	B_PE																																							
	{116 ,0x6000},	  // 74,	SEND_THR_PITCH_DET0 																																	
	{117 ,0x5000},	  // 75,	SEND_THR_PITCH_DET1 																												 
	{118 ,0x4000},	  // 76,	SEND_THR_PITCH_DET2 																											 
	{119 ,0x0008},	  // 77,	PITCH_BFR_LEN,	no mapping																											 
	{120 ,0x0003},	  // 78,	SBD_PITCH_DET,	no mapping																											 
	{121 ,0x0080},	  // 79,	TD_AEC_LEN, 	 no mapping 																											 
	{122 ,0x4000},	  // 7A,	MU0_UNP_TDAEC,	no mapping																											 
	{123 ,0x1000},	  // 7B,	MU0_PTD_TDAEC,	no mapping																											 
	{124 ,0x0100},	  // 7C,	dsp_micgain0 (gain on MIC0 after LAEC)																														
	{125 ,0x0100},	  // 7D,	dsp_micgain1 (gain on MIC1 after LAEC)																														   
	{126 ,0x0000},	  // 7E,	MIC0_BF_DELAY_FRAME, GSC shift 0-2																														 
	{127 ,0x0000},	  // 7F,	PP_RESERV_3 																													   
	{128 ,0x0000},	  // 80,	PP_RESERV_4 																													   
	{129 ,0x0000},	  // 81,	PP_RESERV_5 																													   
	{130 ,0x0000},	  // 82,	PP_RESERV_6 																													   
	{131 ,0x0000},	  // 83,	PP_RESERV_7 																													   
	{132 ,0x0040},	  // 84,	FRQ_AEC_LENGTH																														 
	{133 ,0x0800},	  // 85,	AEC_REF_GAIN, Q11																												 
	{134 ,0x1000},	  // 86,	THR_RE_EST																														 
	{135 ,0x4000},	  // 87,	EAD_THRD																														 
	{136 ,0x2000},	  // 88,	MIN_EQ_RE_EST0																													 
	{137 ,0x2000},	  // 89,	MIN_EQ_RE_EST1																													 
	{138 ,0x2000},	  // 8A,	MIN_EQ_RE_EST2																													 
	{139 ,0x2000},	  // 8B,	MIN_EQ_RE_EST3																													 
	{140 ,0x2000},	  // 8C,	MIN_EQ_RE_EST4																													 
	{141 ,0x2000},	  // 8D,	MIN_EQ_RE_EST5																													 
	{142 ,0x2000},	  // 8E,	MIN_EQ_RE_EST6																													 
	{143 ,0x2000},	  // 8F,	MIN_EQ_RE_EST7																													 
	{144 ,0x2000},	  // 90,	MIN_EQ_RE_EST8																													 
	{145 ,0x2000},	  // 91,	MIN_EQ_RE_EST9																													 
	{146 ,0x2000},	  // 92,	MIN_EQ_RE_EST10 																												 
	{147 ,0x2000},	  // 93,	MIN_EQ_RE_EST11 																												 
	{148 ,0x2000},	  // 94,	MIN_EQ_RE_EST12 																												 
	{149 ,0x4000},	  // 95,	LAMBDA_RE_EST																													 
	{150 ,0x4000},	  // 96,	LAMBDA_CB_NLE																													 
	{151 ,0x0200},	  // 97,	C_POST_FLT																														 
	{152 ,0x0100},	  // 98,	GAIN_NP 																														 
	{153 ,0x0032},	  // 99,	SE_HOLD_N																														 
	{154 ,0x0000},	  // 9A,	AEC_MIC_DELAY_LENGTH ; //Range: [0~ 160*7] sample																											 
	{155 ,0x0000},	  // 9B,	AEC_REF_DELAY_LENGTH ; //Range: [0~ 160*7] sample																											
	{156 ,0x0000},	  // 9C,	Reserved																									  
	{157 ,0x0000},	  // 9D,	Reserved																									  
	{158 ,0x0000},	  // 9E,	Reserved																									  
	{159 ,0x0000},	  // 9F,	Reserved																									  
	{160 ,0x7FFF},	  // A0,	Reserved																									  
	{161 ,0x0000},	  // A1,	  Reserved																										
	{162 ,0x0008},	  // A2,	Reserved																									  
	{163 ,0x7FFF},	  // A3,	Reserved																									  
	{164 ,0x7000},	  // A4,	MU0_UNP_FRQ_AEC 																													
	{165 ,0x3000},	  // A5,	MU0_PTD_FRQ_AEC 																													
	{166 ,0x6666},	  // A6,	Reserved																											
	{167 ,0x0148},	  // A7,	Reserved																										   
	{168 ,0x000A},	  // A8,	MINENOISETH 																														
	{169 ,0x0800},	  // A9,	MU0_RE_EST																															
	{170 ,0x0001},	  // AA,	Reserved																									
	{171 ,0x0000},	  // AB,	Reserved																									
	{172 ,0x4000},	  // AC,	Reserved																											 
	{173 ,0x000A},	  // AD,	FEBIG_VAD_THRD																														 
	{174 ,0x7000},	  // AE,	DTRATIO_FACTOR_FEBIG																													   
	{175 ,0x7000},	  // AF,	DT_HMNC_RTO 																													  
	{176 ,0x4000},	  // B0,	DT_HMNC_RTO_RCV 																													  
	{177 ,0x4000},	  // B1,	DT_HMNC_MAXE																													   
	{178 ,0x7FFF},	  // B2,	B_LESSCUT_RTO_ECHO																														  
	{179 ,0x0000},	  // B3,	EC_RESERV_7 																													  
	{180 ,0x0000},	  // B4,	EC_RESERV_8 																													  
	{181 ,0x0000},	  // B5,	EC_RESERV_9 																													  
	{182 ,0x0028},	  // B6,	DT_HOLD_N																														
	{183 ,0x4000},	  // B7,	DTD_THR10																														
	{184 ,0x4000},	  // B8,	DTD_THR11																														
	{185 ,0x4000},	  // B9,	DTD_THR12																														
	{186 ,0x4000},	  // BA,	DTD_THR13																														
	{187 ,0x4000},	  // BB,	DTD_THR14																														
	{188 ,0x6000},	  // BC,	DTD_THR15																														
	{189 ,0x6000},	  // BD,	DTD_THR16																														
	{190 ,0x2000},	  // BE,	DTD_THR20																														
	{191 ,0x2000},	  // BF,	DTD_THR21																														
	{192 ,0x4000},	  // C0,	DTD_THR22																														
	{193 ,0x4000},	  // C1,	DTD_THR23																														
	{194 ,0x4000},	  // C2,	DTD_THR24																														
	{195 ,0x6000},	  // C3,	DTD_THR25																														
	{196 ,0x6000},	  // C4,	DTD_THR26																														
	{197 ,0x7FFF},	  // C5,	DTD_THR3																														
	{198 ,0x0000},	  // C6,	SPK_CUT_K																														
	{199 ,0x1F40},	  // C7,	DT_CUT_K																														
	{200 ,0x0000},	  // C8,	DT_CUT_THR																														
	{201 ,0x04EB},	  // C9,	Reserved																								 
	{202 ,0x0000},	  // CA,	Reserved																								   
	{203 ,0x01F4},	  // CB,	Reserved																									  
	{204 ,0x4000},	  // CC,	Reserved																									  
	{205 ,0x0000},	  // CD,	Reserved																								   
	{206 ,0x0000},	  // CE,	LFVAD_LPF_INDEX: [0,4], 0: 120Hz,  1: 180Hz,  2: 210Hz,  3: 270Hz,	4:330Hz 														
	{207 ,0x1000},	  // CF,	LF_VAD_THRD 																														
	{208 ,0x0300},	  // D0,	LF_VAD_NOISE_THRD																													
	{209 ,0x0000},	  // D1,	DT_RESERV_3 																													  
	{210 ,0x0000},	  // D2,	DT_RESERV_4 																													  
	{211 ,0x0040},	//0x0008	// D3,	  LAEC_NORM_GND_INITIAL_ECHO_SUPP
	{212 ,0x0040},	  // D4,	LAEC_NORM_GND(smaller, faster)
	{213 ,0x0000},	  // D5,	DT_RESERV_7 																													  
	{214 ,0x0050},	  // D6,	N1_SN_EST,	in ms																												
	{215 ,0x0010},	  // D7,	N2_SN_EST																														
	{216 ,0x1000},	  // D8,	A_POST_FLT																														
	{217 ,0x1000},	  // D9,	A_POST_FLT_ECHO 																									  
	{218 ,0x0800},	  // DA,	B_POST_FLT																															
	{219 ,0x0800},	  // DB,	B_POST_FLT_ECHO 																									  
	{220 ,0x000A},	  // DC,	NS_level_Control																												
	{221 ,0x0018},	  // DD,	NS_level_Ctrl_1 																													 
	{222 ,0x0015},	  // DE,	NS_level_Ctrl_2 																													 
	{223 ,0x0018},	  // DF,	NS_level_Ctrl_3,																										  
	{224 ,0x0014},	  // E0,	NS_level_Ctrl_4,																										  
	{225 ,0x0014},	  // E1,	NS_level_Ctrl_5,																										  
	{226 ,0x0019},	  // E2,	NS_level_Ctrl_6,																										  
	{227 ,0x0019},	  // E3,	NS_level_Ctrl_7,																										  
	{228 ,0x0000},	  // E4,	DELTA_THR_SN_EST																													
	{229 ,0x0000},	  // E5,	DELTA_THR_SN_EST_1, 																									  
	{230 ,0x0200},	  // E6,	DELTA_THR_SN_EST_2, 																									  
	{231 ,0x0200},	  // E7,	DELTA_THR_SN_EST_3, 																									  
	{232 ,0x0200},	  // E8,	DELTA_THR_SN_EST_4, 																									  
	{233 ,0x0200},	  // E9,	DELTA_THR_SN_EST_5, 																									  
	{234 ,0x0200},	  // EA,	DELTA_THR_SN_EST_6, 																									  
	{235 ,0x0200},	  // EB,	DELTA_THR_SN_EST_7, 																									  
	{236 ,0xF800},	  // EC,	THR_SN_EST																															
	{237 ,0xFB00},	  // ED,	THR_SN_EST_1,																											   
	{238 ,0xFA00},	  // EE,	THR_SN_EST_2,																											   
	{239 ,0xF800},	  // EF,	THR_SN_EST_3,																											   
	{240 ,0xF800},	  // F0,	THR_SN_EST_4,																											   
	{241 ,0xF800},	  // F1,	THR_SN_EST_5,																											   
	{242 ,0xFB00},	  // F2,	THR_SN_EST_6,																											   
	{243 ,0xFB00},	  // F3,	THR_SN_EST_7,																											   
	{244 ,0x1000},	  // F4,	A_POST_FILT_S_0 																													 
	{245 ,0x1000},	  // F5,	A_POST_FILT_S_1 																													 
	{246 ,0x6000},	  // F6,	A_POST_FILT_S_2 																													 
	{247 ,0x6000},	  // F7,	A_POST_FILT_S_3,																										   
	{248 ,0x6000},	  // F8,	A_POST_FILT_S_4,																										   
	{249 ,0x6000},	  // F9,	A_POST_FILT_S_5,																										   
	{250 ,0x7FFF},	  // FA,	A_POST_FILT_S_6,																										   
	{251 ,0x6000},	  // FB,	A_POST_FILT_S_7,																										   
	{252 ,0x7A00},	  // FC,	LAMBDA_PFILT_S_0																													 
	{253 ,0x7B00},	  // FD,	LAMBDA_PFILT_S_1																													 
	{254 ,0x7B00},	  // FE,	LAMBDA_PFILT_S_2																													 
	{255 ,0x7B00},	  // FF,	LAMBDA_PFILT_S_3,																										
	{256 ,0x7B00},	  // 100,	 LAMBDA_PFILT_S_4,																										 
	{257 ,0x7B00},	  // 101,	 LAMBDA_PFILT_S_5,																										 
	{258 ,0x7B00},	  // 102,	 LAMBDA_PFILT_S_6,																										 
	{259 ,0x7B00},	  // 103,	 LAMBDA_PFILT_S_7,																										 
	{260 ,0x000A},	  // 104,	 MIN_GAIN_S_0																														  
	{261 ,0x0011},	  // 105,	 MIN_GAIN_S_1																														  
	{262 ,0x000E},	  // 106,	 MIN_GAIN_S_2																														  
	{263 ,0x0012},	  // 107,	 MIN_GAIN_S_3,																											  
	{264 ,0x000F},	  // 108,	 MIN_GAIN_S_4,																											  
	{265 ,0x000F},	  // 109,	 MIN_GAIN_S_5,																											  
	{266 ,0x0014},	  // 10A,	 MIN_GAIN_S_6,																											  
	{267 ,0x000F},	  // 10B,	 MIN_GAIN_S_7,																											  
	{268 ,0x0000},	  // 10C,	 BF_SGRAD_FLG																													 
	{269 ,0x0001},	  // 10D,	 HMNC_BST_FLG,																										  
	{270 ,0x0800},	  // 10E,	 HMNC_BST_THR,																										  
	{271 ,0x0000},	  // 10F,	 K_PEPPER																													  
	{272 ,0x1000},	  // 110,	 A_PEPPER																														 
	{273 ,0x7E10},	  // 111,	 SEND_LAMBDA_PFLT																												 
	{274 ,0x000A},	  // 112,	 SN_C_F,  in dB unit																											 
	{275 ,0x0008},	  // 113,	 K_APT, 																												   
	{276 ,0x6000},	  // 114,	 LAMBDA_NN_EST, 																									 
	{277 ,0x0000},	  // 115,	 NOISEDET																															  
	{278 ,0x00A0},	  // 116,	 NOISE_TH_0 																														  
	{279 ,0x05DC},	  // 117,	 NOISE_TH_1 																														  
	{280 ,0x0320},	  // 118,	 NOISE_TH_2 																													   
	{281 ,0x32C8},	  // 119,	 NOISE_TH_3 																													   
	{282 ,0x6987},	  // 11A,	 NOISE_TH_4 																													   
	{283 ,0x7FFF},	  // 11B,	 NMOS_SUP,																											   
	{284 ,0x7FFF},	  // 11C,	 SNRI_SUP_0,																											
	{285 ,0x7FFF},	  // 11D,	 SNRI_SUP_1,																											
	{286 ,0x5000},	  // 11E,	 SNRI_SUP_2,																											
	{287 ,0x5000},	  // 11F,	 SNRI_SUP_3,																											
	{288 ,0x7000},	  // 120,	 SNRI_SUP_4,																											
	{289 ,0x7000},	  // 121,	 SNRI_SUP_5,																											
	{290 ,0x2000},	  // 122,	 SNRI_SUP_6,																											
	{291 ,0x4000},	  // 123,	 SNRI_SUP_7,																											
	{292 ,0x0190},	  // 124,	 NDETCT, Convergence time ms																														
	{293 ,0x0014},	  // 125,	 MINENOISE_MIC0_TH, 																										 
	{294 ,0x0258},	  // 126,	 OUT_ENER_S_TH_CLEAN,																								 
	{295 ,0x0258},	  // 127,	 OUT_ENER_S_TH_LESSCLEAN,																								
	{296 ,0x0190},	  // 128,	 OUT_ENER_S_TH_NOISEY,																									
	{297 ,0x019A},	  // 129,	 OUT_ENER_TH_NOISE, 																									
	{298 ,0x0200},	  // 12A,	 OUT_ENER_TH_SPEECH,																								   
	{299 ,0x0000},	  // 12B,	 SN_NPB_GAIN,  no Mapping																										   
	{300 ,0x0000},	  // 12C,	 NN_NPB_GAIN,  no Mapping																										   
	{301 ,0x0003},	  // 12D,	 INBEAM_T																															 
	{302 ,0x0043},	  // 12E,	 INBEAM_HOLD_T																														 
	{303 ,0x7FFF},	  // 12F,	 G_STRICT_INBEAM:  3.0,  Q13 format 																								 
	{304 ,0x0000},	  // 130,	 THR_LFNS,	no Mapping																											   
	{305 ,0x0000},	  // 131,	 G_LFNS,  no Mapping																											   
	{306 ,0x0000},	  // 132,	 CSX_ALPHA_0,  no Mapping																										   
	{307 ,0x0000},	  // 133,	 CSX_ALPHA_1,  no Mapping																										   
	{308 ,0x0000},	  // 134,	 CSX_ALPHA_2,  no Mapping																										   
	{309 ,0x0000},	  // 135,	 CSX_ALPHA_3,  no Mapping																										   
	{310 ,0x0800},	  // 136,	 MU_ARSP_EST,																													 
	{311 ,0x00C8},	  // 137,	 P_OUTBEAM_MIN_TH,	no Mapping																										  
	{312 ,0x0000},	  // 138,	 EXTRA_NS_L 																														 
	{313 ,0x0800},	  // 139,	 EXTRA_NS_A 																														 
	{314 ,0x0005},	  // 13A,	 VR_NOISE_FLOOR_TH,  no Mapping 																									  
	{315 ,0x7FFF},	  // 13B,	 MIN_G_LOW300HZ 																													 
	{316 ,0x0800},	  // 13C,	 A_PEPPER_HF,  Q10 format																											 
	{317 ,0x1D4C},	  // 13D,	 K_PEPPER_HF,4000Hz(0xFA0)																														   
	{318 ,0x2EE0},	  // 13E,	 NOISE_TH_5 																													  
	{319 ,0x0384},	  // 13F,	 NOISE_TH_6 																													  
	{320 ,0x7FFF},	  // 140,	 NOISE_TH5_2																													   
	{321 ,0x7FFF},	  // 141,	 NOISE_TH0_2																													   
	{322 ,0x7FFF},	  // 142,	 NOISE_TH0_3																													   
	{323 ,0x012C},	  // 143,	 MINENOISE_MIC0_S_TH																													   
	{324 ,0x00C8},	  // 144,	 ENOISE_MIC0_TH 																													  
	{325 ,0x6666},	  // 145,	 NASSA_FQ_EQUAL_GAIN_SEND0 //B_POST_FILT_T1 																												   
	{326 ,0x6666},	  // 146,	 NASSA_FQ_EQUAL_GAIN_SEND1 //B_POST_FILT_T2 																													 
	{327 ,0x6666},	  // 147,	 NASSA_FQ_EQUAL_GAIN_SEND2 //B_POST_FILT_T3 																													 
	{328 ,0x6666},	  // 148,	 NASSA_FQ_EQUAL_GAIN_SEND3 //B_POST_FILT_T4 																													 
	{329 ,0x6666},	  // 149,	 NASSA_FQ_EQUAL_GAIN_SEND4 //B_POST_FILT_T5 																													
	{330 ,0x6666},	  // 14A,	 NASSA_FQ_EQUAL_GAIN_SEND5 //B_POST_FILT_T6 																													
	{331 ,0x0028},	  // 14B,	 NASSA_MIN_G  //B_POST_FILT_T7																														 
	{332 ,0x0028},	  // 14C,	 NASSA_MIN_G_1	//NMOS_SUP_MENSA																													   
	{333 ,0x0001},	  // 14D,	 NASSA_GAIN_TYPE  //NS_PATCH_SELECT 																											  
	{334 ,0x09C4},	  // 14E,	 GAIN0_NTH																														   
	{335 ,0x0CCD},	  // 14F,	 MUSIC_MORENS																														 
	{336 ,0x0000},	  // 150,	 NS_RESERV_20																													   
	{337 ,0x0000},	  // 151,	 NS_RESERV_21
	{338 ,0x0000},	  // 152,	 NS_RESERV_22
	{339 ,0x0000},	  // 153,	 NS_RESERV_23
	{340 ,0x0000},	  // 154,	 NS_RESERV_24
	{341 ,0x0000},	  // 155,	 NS_RESERV_25
	{342 ,0x0000},	  // 156,	 NS_RESERV_26
	{343 ,0x0C00},	  // 157,	 RHO_UPB																														 
	{344 ,0x0BB8},	  // 158,	 N_HOLD_HS																														 
	{345 ,0x001E},	  // 159,	 no mapping 																											 
	{346 ,0x0000},	  // 15A,	 no mapping 																										
	{347 ,0x1000},	  // 15B,	 MIC_BLOCK_FACTOR,	no mapping																										  
	{348 ,0x7FFF},	  // 15C,	 LAMBDA_ARSP_EST																												 
	{349 ,0x0000},	  // 15D,	 NSEST_BFRLRNRDC,  no mapping																										  
	{350 ,0x0000},	  // 15E,	 no mapping 																										
	{351 ,0x2000},	  // 15F,	 THR_STD_NSR																														  
	{352 ,0x056C},	  // 160,	 N_HOLD_STD 																														  
	{353 ,0x019A},	  // 161,	 STD_THR_PLH																														  
	{354 ,0x0CCD},	  // 162,	 THR_STD_RHO																														  
	{355 ,0x0010},	  // 163,	 HS_VAD_BIN,  no Mapping																											  
	{356 ,0x2666},	  // 164,	 THRD_VAD_HS,  no Mapping																											  
	{357 ,0x2CCD},	  // 165,	 MEAN_RHO_MIN_TH2,	no Mapping																										  
	{358 ,0x0032},	  // 166,	 SILENCE_T,  no Mapping 																											  
	{359 ,0x3800},	  // 167,	 B_LESSCUT_RHO_S,																										   
	{360 ,0x7FFF},	  // 168,	 B_LESSCUT_RHO_S_CAR,																									   
	{361 ,0x7FFF},	  // 169,	 B_LESSCUT_RHO_S_PUB,																									  
	{362 ,0x7FFF},	  // 16A,	 B_LESSCUT_RHO_S_ROAD,																									   
	{363 ,0x7FFF},	  // 16B,	 B_LESSCUT_RHO_S_TRAIN,  
	{364 ,0x7FFF},	  // 16C,	 B_LESSCUT_RHO_S_CAFE																														
	{365 ,0x7FFF},	  // 16D,	 B_LESSCUT_RHO_S_PINK																														
	{366 ,0x7FFF},	  // 16E,	 B_LESSCUT_RHO_S_MUSIC																														 
	{367 ,0x0000},	  // 16F,	 HS_RESERV_4																													   
	{368 ,0x0000},	  // 170,	 HS_RESERV_5																													   
	{369 ,0x0000},	  //  171,	 HS_RESERV_6
	{370 ,0x0000},	  //  172,	 HS_RESERV_7
	{371 ,0x0000},	  // 173,	 HS_RESERV_8																													   
	{372 ,0x0000},	  // 174,	 HS_RESERV_9																													   
	{373 ,0x0000},	  // 175,	 HS_RESERV_10																													   
	{374 ,0x0000},	  // 176,	 HS_RESERV_11																													   
	{375 ,0x0000},	  // 177,	 HS_RESERV_12																													   
	{376 ,0x003C},	  // 178,	 DOA_VAD_THR0_0 																												 
	{377 ,0x003C},	  // 179,	 DOA_VAD_THR0_1  Reserved																													 
	{378 ,0x003C},	  // 17A,	 DOA_VAD_THR1_0 																												 
	{379 ,0x003C},	  // 17B,	 DOA_VAD_THR1_1  Reserved																													 
	{380 ,0x0000},	  // 17C,	 SRC_DOA_RNG_Low_0A 																											 
	{381 ,0x00B4},	  // 17D,	 SRC_DOA_RNG_High_0A																											 
	{382 ,0x005A},	  // 17E,	 DFLT_SRC_DOA_0A																												 
	{383 ,0x0000},	  // 17F,	 SRC_DOA_RNG_Low_0B  Reserved																											 
	{384 ,0x0000},	  // 180,	 SRC_DOA_RNG_High_0B Reserved																											 
	{385 ,0x0000},	  // 181,	 DFLT_SRC_DOA_0B	 Reserved																											 
	{386 ,0x0000},	  // 182,	 SRC_DOA_RNG_Low_0C  Reserved																											 
	{387 ,0x0000},	  // 183,	 SRC_DOA_RNG_High_0C Reserved																											 
	{388 ,0x0000},	  // 184,	 DFLT_SRC_DOA_0C	 Reserved																											 
	{389 ,0x0000},	  // 185,	 SRC_DOA_RNG_Low_0D  Reserved																											 
	{390 ,0x0000},	  // 186,	 SRC_DOA_RNG_High_0D Reserved																											 
	{391 ,0x0000},	  // 187,	 DFLT_SRC_DOA_0D	 Reserved																											 
	{392 ,0x0078},	  // 188,	 SRC_DOA_RNG_Low_1A  Reserved																											 
	{393 ,0x00B4},	  // 189,	 SRC_DOA_RNG_High_1A Reserved																											 
	{394 ,0x0096},	  // 18A,	 DFLT_SRC_DOA_1A	 Reserved																											 
	{395 ,0x0000},	  // 18B,	 SRC_DOA_RNG_Low_1B  Reserved																											 
	{396 ,0x003C},	  // 18C,	 SRC_DOA_RNG_High_1B Reserved																											 
	{397 ,0x001E},	  // 18D,	 DFLT_SRC_DOA_1B	 Reserved																											 
	{398 ,0x0000},	  // 18E,	 SRC_DOA_RNG_Low_1C  Reserved																											 
	{399 ,0x0000},	  // 18F,	 SRC_DOA_RNG_High_1C Reserved																											 
	{400 ,0x0000},	  // 190,	 DFLT_SRC_DOA_1C	 Reserved																											 
	{401 ,0x0000},	  // 191,	 SRC_DOA_RNG_Low_1D  Reserved																											 
	{402 ,0x0000},	  // 192,	 SRC_DOA_RNG_High_1D Reserved																											 
	{403 ,0x0000},	  // 193,	 DFLT_SRC_DOA_1D	 Reserved																											 
	{404 ,0x0172},	  // 194,	 BF_HoldOff_T																													 
	{405 ,0x7FFF},	  // 195,	 DOA_COST_FACTOR,																										   
	{406 ,0x4000},	  // 196,	 MAIN2REF_RATIO_TH0,																									  
	{407 ,0x071C},	  // 197,	 DOA_TRK_THR,  no Mapping																											  
	{408 ,0x012C},	  // 198,	 N_HOLD_DOA,  no Mapping																											  
	{409 ,0x0040},	  // 199,	 N1_HOLD_HF 																														  
	{410 ,0x0040},	  // 19A,	 N2_HOLD_HF 																														  
	{411 ,0x2000},	  // 19B,	 BF_Reset_THR_HF																												 
	{412 ,0x0000},	  // 19C,	 DOA_SMOOTH,  no Mapping																											  
	{413 ,0x0200},	  // 19D,	 MU_BF																																  
	{414 ,0x0800},	  // 19E,	 MU_BF_LF_B2,  no Mapping																											  
	{415 ,0x0040},	  // 19F,	 BF_FC_ENDBIN_B2,  no Mapping																										  
	{416 ,0x0020},	  // 1A0,	 BF_FC_ENDBIN,	no Mapping																											  
	{417 ,0x1000},	  // 1A1,	 B_POST_INITIAL_ECHO_SUPP																								
	{418 ,0x4000},	  // 1A2,	 C_POST_INITIAL_ECHO_SUPP
	{419 ,0x0000},	  // 1A3,	 Reserved																										   
	{420 ,0x1000},	  // 1A4,	 B_POST_MAXB_INITIAL_ECHO_SUPP
	{421 ,0x0078},	  // 1A5,	 BF_HOLDOFF_T2,  no Mapping 																										  
	{422 ,0x038E},	  // 1A6,	 DELTA_SRC_DOA_RNG,  no Mapping 																									  
	{423 ,0x2000},	  // 1A7,	 MU_BF_LF,	no Mapping																												  
	{424 ,0x3800},	//0x4E20	// 1A8,    XAXBRATIO_TH_L  ref/main ratio																											
	{425 ,0x00F0},	  // 1A9,	 SPEECHKEEP_ENDBIN	//DFLT_SRC_LOC_1,  no Mapping																										   
	{426 ,0x2000},	  // 1AA,	 MU_BF_ADPTNS  //DFLT_SRC_LOC_2,  no Mapping																										  
	{427 ,0x038E},	  // 1AB,	 DOA_TRACK_VADTH,  no Mapping																										  
	{428 ,0x0000},	  // 1AC,	 DOA_TRACK_NEW,  no Mapping   
	{429 ,0x0005},	  // 1AD,	 out_ener_th_speech 							 
	{430 ,0x0002},	  // 1AE,	 out_ener_th_noise								
	{431 ,0x7FFF},	  // 1AF,	 SMALL_NOISE_SUP									   
	{432 ,0x7fff},	  // 1B0,	 SMASKGNS												 
	{433 ,0x4000},	  // 1B1,	 SMALL_NOISE_SUP_ALPHA_UNIT 												 
	{434 ,0x0005},	  // 1B2,	 SN_INBEAM_HOLD_T						   
	{435 ,0x6C50},	  // 1B3,	 NOISE_SUP_ALPHA_DOWN					 
	{436 ,0x7D71},	  // 1B4,	 NOISE_SUP_ALPHA_UP 						   
	{437 ,0x0005},	  // 1B5,	 COMFORT_NOISE_GAIN 																													  
	{438 ,0x0000},	  // 1B6,	 mic0_delay_sample; //Notused
	{439 ,0x0000},	  // 1B7,	 mic1_delay_sample; //Notused																												 
	{440 ,0x0000},	  // 1B8,	 MASK_2ND																													  
	{441 ,0x0400},	  // 1B9,	 SSA4_MAG_MIC_GAIN																																	  
	{442 ,0x0100},	  // 1BA,	 SSA4_MAG_ECHO_GAIN 																													 
	{443 ,0x0000},	  // 1BB,	 DPCRN_MASK_MORENS																														
	{444 ,0x0000},	  // 1BC,	 DPCRN_MASK_MORENS_ECHO 																													 
	{445 ,0x0400},	  // 1BD,	 SSA4_MAG_MIC_GAIN_INIT 																													
	{446 ,0x2000},	  // 1BE,	 SSA4_UseEstecho_thrd																													   
	{447 ,0x0000},	  // 1BF,	 HF_RESERV_18																													   
	{448 ,0x0000},	  // 1C0,	 HF_RESERV_19																													   
	{449 ,0x0000},	  // 1C1,	 HF_RESERV_20																																																																   
	{450 ,0x0000},	  // 1C2,	 HF_RESERV_21																													   
	{451 ,0x0000},	  // 1C3,	 HF_RESERV_22																																																																			   
	{452 ,0x0000},	  // 1C4,	 HF_RESERV_23																													   
	{453 ,0x0000},	  // 1C5,	 HF_RESERV_24																																																																				   
	{454 ,0x0002},	  // 1C6,	 DERVB_LEN0:	   [0,4]																											 
	{455 ,0x0003},	  // 1C7,	 DERVB_LEN1:	   [DERVB_LEN0, 5]																																																															   
	{456 ,0x7FFF},	  // 1C8,	 RHO_DERVB																															 
	{457 ,0x0000},	  // 1C9,	 MIC_INDX_DERVB 																																																																				   
	{458 ,0x0800},	  // 1CA,	 MU_DERVB																															 
	{459 ,0x0000},	  // 1CB,	 DR_RESERV_0																													   
	{460 ,0x0000},	  // 1CC,	 DR_RESERV_1																													   
	{461 ,0x0000},	  // 1CD,	 DR_RESERV_2																													   
	{462 ,0x0000},	  // 1CE,	 DR_RESERV_3																													   
	{463 ,0x0000},	  // 1CF,	 DR_RESERV_4																													   
	{464 ,0x0000},	  // 1D0,	 DR_RESERV_5																													   
	{465 ,0x0000},	  // 1D1,	 DR_RESERV_6																													   
	{466 ,0x0000},	  // 1D2,	 DR_RESERV_7																													   
	{467 ,0x03E8},	  // 1D3,	 WNS_ENGY_TH,  no Mapping																											  
	{468 ,0x399A},	  // 1D4,	 WIND_COR_TH																														 
	{469 ,0x001E},	  // 1D5,	 WIND_PFGAIN:	  in dB.																											 
	{470 ,0x0028},	  // 1D6,	 SNR_HIGH_TH:	   40.0, Q0 format																									 
	{471 ,0x0CCD},	  // 1D7,	 ZPW_WIND_RTO_TH:  16.0, Q5 format																									 
	{472 ,0x1770},	  // 1D8,	 WIND_COR_HIGH_TH																													 
	{473 ,0x6000},	  // 1D9,	 ZPW_WIND_RTO_TH2																													 
	{474 ,0x0000},	  // 1DA,	 WNS_RESERV_0																													   
	{475 ,0x0000},	  // 1DB,	 WNS_RESERV_1																													   
	{476 ,0x0000},	  // 1DC,	 WNS_RESERV_2																													   
	{477 ,0x0000},	  // 1DD,	 WNS_RESERV_3																													   
	{478 ,0x0000},	  // 1DE,	 WNS_RESERV_4																													   
	{479 ,0x0000},	  // 1DF,	 WNS_RESERV_5																													   
	{480 ,0x0000},	  // 1E0,	 B_POST_FLT_LESS_CUT,  no Mapping																									  
	{481 ,0x0070},	  // 1E1,	 BF_LESSCUT_BBIN,  no Mapping																										  
	{482 ,0x0070},	  // 1E2,	 BF_LESSCUT_EBIN,  no Mapping																										  
	{483 ,0x0010},	  // 1E3,	 POSTBFB0,	no Mapping																												  
	{484 ,0x0070},	  // 1E4,	 POSTBF_BGN,  no Mapping																											  
	{485 ,0x00B0},	  // 1E5,	 POSTBF_END,  no Mapping																											  
	{486 ,0x0E66},	  // 1E6,	 SPEECH_SNR_TH,  no Mapping 																										  
	{487 ,0x0050},	  // 1E7,	 MAX_PRI_SNR_TH,  no Mapping																										  
	{488 ,0x770A},	  // 1E8,	 MAX_PRI_SNR_TH_L,	no Mapping																										  
	{489 ,0x0000},	  // 1E9,	 OUT_ENER_POSTBF_TH,  no Mapping																									  
	{490 ,0x1D9A},	  // 1EA,	 MAIN2REF_RATIO_TH,  no Mapping 																									  
	{491 ,0x0000},	  // 1EB,	 PB_RESRV_0 																													   
	{492 ,0x0000},	  // 1EC,	 PB_RESRV_1 																													   
	{493 ,0x0000},	  // 1ED,	 PB_RESRV_2,   Reserved PFGAIN																									   
	{494 ,0x6666},	  // 1EE,	 FQ_EQUAL_GAIN_SEND0  forLout																											
	{495 ,0x6666},	  // 1EF,	 FQ_EQUAL_GAIN_SEND1																											 
	{496 ,0x6666},	  // 1F0,	 FQ_EQUAL_GAIN_SEND2																											 
	{497 ,0x6666},	  // 1F1,	 FQ_EQUAL_GAIN_SEND3																											 
	{498 ,0x6666},	  // 1F2,	 FQ_EQUAL_GAIN_SEND4																											 
	{499 ,0x6666},	  // 1F3,	 FQ_EQUAL_GAIN_SEND5																											 
	{500 ,0x6666},	  // 1F4,	 FQ_EQUAL_GAIN_SEND6  for 32K																											  
	{501 ,0x6666},	  // 1F5,	 FQ_EQUAL_GAIN_SEND7  for 32K																											 
	{502 ,0x6666},	  // 1F6,	 FQ_EQUAL_SEND_MIC0_GAIN0 forMIC0
	{503 ,0x6666},	  // 1F7,	 FQ_EQUAL_SEND_MIC0_GAIN1																																  
	{504 ,0x6666},	  // 1F8,	 FQ_EQUAL_SEND_MIC0_GAIN2																																  
	{505 ,0x6666},	  // 1F9,	 FQ_EQUAL_SEND_MIC0_GAIN3																																  
	{506 ,0x6666},	  // 1FA,	 FQ_EQUAL_SEND_MIC0_GAIN4																																  
	{507 ,0x6666},	  // 1FB,	 FQ_EQUAL_SEND_MIC0_GAIN5																																  
	{508 ,0x6666},	  // 1FC,	 FQ_EQUAL_SEND_MIC0_GAIN6																																  
	{509 ,0x6666},	  // 1FD,	 FQ_EQUAL_SEND_MIC0_GAIN7																																  
	{510 ,0x6666},	  // 1FE,	 FQ_EQUAL_SEND_MIC1_GAIN0 for MIC1																																  
	{511 ,0x6666},	  // 1FF,	 FQ_EQUAL_SEND_MIC1_GAIN1																																 
	{512 ,0x6666},	  // 200,	 FQ_EQUAL_SEND_MIC1_GAIN2																																 
	{513 ,0x6666},	  // 201,	 FQ_EQUAL_SEND_MIC1_GAIN3																																 
	{514 ,0x6666},	  // 202,	 FQ_EQUAL_SEND_MIC1_GAIN4																																 
	{515 ,0x6666},	  // 203,	 FQ_EQUAL_SEND_MIC1_GAIN5																																 
	{516 ,0x6666},	  // 204,	 FQ_EQUAL_SEND_MIC1_GAIN6																																				  
	{517 ,0x6666},	  // 205,	 FQ_EQUAL_SEND_MIC1_GAIN7																												
	{518 ,0x0000},	  // 206,	 Reserved																													
	{519 ,0x0000},	  // 207,	 Reserved																													
	{520 ,0x0000},	  // 208,	 Reserved																													
	{521 ,0x0000},	  // 209,	 Reserved																													
	{522 ,0x0000},	  // 20A,	 Reserved																													
	{523 ,0x0000},	  // 20B,	 Reserved																													
	{524 ,0x0000},	  // 20C,	 Reserved																													
	{525 ,0x0000},	  // 20D,	 Reserved																													
	{526 ,0x0000},	  // 20E,	 Reserved																													
	{527 ,0x0000},	  // 20F,	 Reserved																													
	{528 ,0x0000},	  // 210,	 Reserved																													
	{529 ,0x0000},	  // 211,	 Reserved																													
	{530 ,0x0000},	  // 212,	 Reserved																													
	{531 ,0x0000},	  // 213,	 Reserved																													
	{532 ,0x0000},	  // 214,	 Reserved																													
	{533 ,0x0000},	  // 215,	 Reserved																													
	{534 ,0x0000},	  // 216,	 Reserved																													
	{535 ,0x0000},	  // 217,	 Reserved																													
	{536 ,0x0000},	  // 218,	 Reserved																													
	{537 ,0x0000},	  // 219,	 Reserved																													
	{538 ,0x0000},	  // 21A,	 Reserved																												
	{539 ,0x0000},	  // 21B,	 Reserved																												
	{540 ,0x0000},	  // 21C,	 Reserved																												
	{541 ,0x0000},	  // 21D,	 Reserved																												
	{542 ,0x0000},	  // 21E,	 Reserved																												
	{543 ,0x0000},	  // 21F,	 Reserved																												
	{544 ,0x0000},	  // 220,	 Reserved																												
	{545 ,0x0000},	  // 221,	 Reserved																												
	{546 ,0x0000},	  // 222,	 Reserved																												
	{547 ,0x0000},	  // 223,	 Reserved																												
	{548 ,0x0000},	  // 224,	 Reserved																												
	{549 ,0x0000},	  // 225,	 Reserved																												
	{550 ,0x0006},	  // 226,	 Reserved																											  
	{551 ,0x2000},	  // 227,	 Reserved																								   
	{552 ,0x6060},	  // 228,	 Reserved																							 
	{553 ,0x7070},	  // 229,	 Reserved																								   
	{554 ,0x0000},	  // 22A,	 Reserved																								
	{555 ,0x0000},	  // 22B,	 Reserved																								
	{556 ,0x4050},	  // 22C,	 Reserved																								 
	{557 ,0x4040},	  // 22D,	 Reserved																								   
	{558 ,0x0000},	  // 22E,	 Reserved																								   
	{559 ,0x0000},	  // 22F,	 Reserved																								   
	{560 ,0x0603},	  // 230,	 Reserved																								   
	{561 ,0x0C09},	  // 231,	 Reserved																								   
	{562 ,0x0000},	  // 232,	 Reserved																								   
	{563 ,0x0000},	  // 233,	 Reserved																								   
	{564 ,0x0000},	  // 234,	 Reserved																								   
	{565 ,0x0000},	  // 235,	 Reserved																								   
	{566 ,0x0000},	  // 236,	 Reserved																								   
	{567 ,0x0000},	  // 237,	 Reserved																								   
	{568 ,0x0000},	  // 238,	 Reserved																								   
	{569 ,0x0000},	  // 239,	 Reserved																									  
	{570 ,0x0000},	  // 23A,	 Reserved																									 
	{571 ,0x0000},	  // 23B,	 Reserved																									 
	{572 ,0x0000},	  // 23C,	 Reserved																									 
	{573 ,0x0000},	  // 23D,	 Reserved																									 
	{574 ,0x0000},	  // 23E,	 Reserved																									 
	{575 ,0x0000},	  // 23F,	 Reserved																									 
	{576 ,0x0000},	  // 240,	 Reserved																									 
	{577 ,0x0000},	  // 241,	 Reserved																									 
	{578 ,0x0000},	  // 242,	 SND_FDDRC_RESERV_0 																											   
	{579 ,0x0000},	  // 243,	 SND_FDDRC_RESERV_1 																											   
	{580 ,0x0000},	  // 244,	 SND_FDDRC_RESERV_2 																											   
	{581 ,0x0000},	  // 245,	 SND_FDDRC_RESERV_3 																											   
	{582 ,0x0000},	  // 246,	 SND_FDDRC_RESERV_4 																											   
	{583 ,0x0000},	  // 247,	 SND_FDDRC_RESERV_5 																											   
	{584 ,0x0000},	  // 248,	 SND_FDDRC_RESERV_6 																											   
	{585 ,0x0000},	  // 249,	 SND_FDDRC_RESERV_7 																											   
	{586 ,0x0000},	  // 24A,	 SND_FDDRC_RESERV_8 																											   
	{587 ,0x0000},	  // 24B,	 SND_FDDRC_RESERV_9 																											   
	{588 ,0x0000},	  // 24C,	 SND_FDDRC_RESERV_10																											   
	{589 ,0x0000},	  // 24D,	 SND_FDDRC_RESERV_11																											   
	{590 ,0x0000},	  // 24E,	 SND_FDDRC_RESERV_12																											   
	{591 ,0x0000},	  // 24F,	 SND_FDDRC_RESERV_13																											   
	{592 ,0x0000},	  // 250,	 SND_FDDRC_RESERV_14																											   
	{593 ,0x0000},	  // 251,	 SND_FDDRC_RESERV_15																											   
	{594 ,0x0000},	  // 252,	 SND_FDDRC_RESERV_16																											   
	{595 ,0x0000},	  // 253,	 SND_FDDRC_RESERV_17																											   
	{596 ,0x0000},	  // 254,	 SND_FDDRC_RESERV_28																											   
	{597 ,0x0000},	  // 255,	 SND_FDDRC_RESERV_19																											   
	{598 ,0x0000},	  // 256,	 SND_FDDRC_RESERV_20																											   
	{599 ,0x0000},	  // 257,	 SND_FDDRC_RESERV_21																											   
	{600 ,0x0000},	  // 258,	 SND_FDDRC_RESERV_22																											   
	{601 ,0x0000},	  // 259,	 SND_FDDRC_RESERV_23																											   
	{602 ,0x0000},	  // 25A,	 SND_FDDRC_RESERV_24																											   
	{603 ,0x0000},	  // 25B,	 SND_FDDRC_RESERV_25																											   
	{604 ,0x0000},	  // 25C,	 SND_FDDRC_RESERV_26																											   
	{605 ,0x0100},	  // 25D,	 Reserved																								
	{606 ,0x0000},	  // 25E,	 Reserved																									 
	{607 ,0x0000},	  // 25F,	 Reserved																									 
	{608 ,0x0000},	  // 260,	 Reserved																									 
	{609 ,0x0000},	  // 261,	 FFP_START_TH																								   
	{610 ,0x6400},	  // 262,	 FFP_LAMBDA_PKA_FP																											 
	{611 ,0x0F1B},	  // 263,	 FFP_TPKA_FP	-3dB/MICVOL600																													 
	{612 ,0x0400},	  // 264,	 FFP_MIN_G_FP																													 
	{613 ,0x0800},	  // 265,	 FFP_MAX_G_FP																													 
	{614 ,0x001F},	  // 266,	 FFP_K_METAL,  no mapping																										 
	{615 ,0x4000},	  // 267,	 FFP_A_POST_FLT,  no mapping																									 
	{616 ,0x0F5C},	  // 268,	 RHO_OUTBEAM_TH,  no mapping																									 
	{617 ,0x4CCD},	  // 269,	 TPKA_FFP_THD,	no mapping																										 
	{618 ,0x0000},	  // 26A,	 FFP_RESERV_0																													   
	{619 ,0x0000},	  // 26B,	 FFP_RESERV_1																													   
	{620 ,0x0000},	  // 26C,	 FFP_RESERV_2																													   
	{621 ,0x0000},	  // 26D,	 FFP_RESERV_3																													   
	{622 ,0x0000},	  // 26E,	 FFP_RESERV_4																													   
	{623 ,0x0000},	  // 26F,	 FFP_RESERV_5																													   
	{624 ,0x0001},	  // 270,	 LOUT_HPF_FILTER_INDEX																											 
	{625 ,0x0000},	  // 271,	 SEND_DRC_QUIET_TH																												 
	{626 ,0x0000},	  // 272,	 SEND_DRC_DECAY_TH																												 
	{627 ,0x1600},	  // 273,	 SEND_DRC_TH1																													 
	{628 ,0x1A00},	  // 274,	 SEND_DRC_TH2																													 
	{629 ,0x6000},	  // 275,	 SEND_DRC_SLOP1 																												 
	{630 ,0x7800},	  // 276,	 SEND_DRC_SLOP2 																												 
	{631 ,0x4000},	  // 277,	 SEND_DRC_ALPHA_UP																												 
	{632 ,0x7EB8},	  // 278,	 SEND_DRC_ALPHA_DOWN																											 
	{633 ,0x0000},	  // 279,	 SEND_DRC_HMNC_FLAG 																											 
	{634 ,0x0000},	  // 27A,	 SEND_DRC_HMNC_GAIN 																											 
	{635 ,0x0000},	  // 27B,	 SEND_DRC_SMT_FLAG																												 
	{636 ,0x0000},	  // 27C,	 SEND_DRC_SMT_W 																												 
	{637 ,0x0100},	  // 27D,	 MIC_VOLUME_GAIN																													 
	{638 ,0x0000},	  // 27E,	 MIC_VOLUME_GAIN2																												  
	{639 ,0x0000},	  // 27F,	 SEND_DRC_RESERV_1																												   
	{640 ,0x0000},	  // 280,	 SSA_TFMASKLTH
	{641 ,0x0000},	  // 281,	 SSA_TFMASKLTHL
	{642 ,0x0CCD},	  // 282,	 SSA_TFMASKHTH
	{643 ,0x0CCD},	  // 283,	 SSA_TFMASKLTH_BINVAD	
	{644 ,0xF333},	  // 284,	 SSA_TFMASKLTH_NS_EST	
	{645 ,0x2CCD},	  // 285,	 SSA_TFMASKLTH_DOA	
	{646 ,0xECCD},	  // 286,	 SSA_TFMASKTH_BLESSCUT
	{647 ,0x1000},	  // 287,	 SSA_B_LESSCUT_RTO_MASK
	{648 ,0x3800},	  // 288,	 SSA_SB_RHO_MEAN_TH_ABN
	{649 ,0x2000},	  // 289,	 SSA_B_POST_FLT_MASK
	{650 ,0x5333},	  // 28A,	 SSA_GAIN_WIND_MASK
	{651 ,0x7FFF},	  // 28B,	 SSA_TFMASK_BFSTRICT_MUSIC
	{652 ,0x0000},	  // 28C,	 SSA_TFMASK_BFSTRICT_NOMUSIC
	{653 ,0x0000},	  // 28D,	 SND_RESERV_13																													   
	{654 ,0x0000},	  // 28E,	 SND_RESERV_14																													   
	{655 ,0x0000},	  // 28F,	 SND_RESERV_15																													   
	{656 ,0x0000},	  // 290,	 SND_RESERV_16																													   
	{657 ,0x0000},	  // 291,	 SND_RESERV_17																														
	{658 ,0x0000},	  // 292,	 SND_RESERV_18																													   
	{659 ,0x0000},	  // 293,	 SND_RESERV_19																													   
	{660 ,0x0000},	  // 294,	 SND_RESERV_20																													   
	{661 ,0x0000},	  // 295,	 SND_RESERV_21																													   
	{662 ,0x0000},	  // 296,	 SND_RESERV_22																													   
	{663 ,0x0000},	  // 297,	 FRAME_Counter read indicator																													  
	{664 ,0x0000},	  // 298,	SND_RESERV_24		  //LINEOUT_DEBUG_SET																												   
	{665 ,0x0000},	  // 299,	SND_RESERV_25		  //SPK_DEBUG_SET																													   
	{666 ,0x0000},	  // 29A,	SND_RESERV_26		  //MAX_MIC0_READOUT																														  
	{667 ,0x0000},	  // 29B,	SND_RESERV_27		  //MAX_MIC1_READOUT																														  
	{668 ,0x0000},	  // 29C,	SND_RESERV_28		  //MAX_MIC2_READOUT																														  
	{669 ,0x0000},	  // 29D,	SND_RESERV_29		  //MAX_LIN_READOUT 																												   
	{670 ,0x0000},	  // 29E,	SND_RESERV_30		  //MAX_LINEOUT_READOUT 																													  
	{671 ,0x0000},	  // 29F,	SND_RESERV_31		//MAX_SPKOUT_READOUT																														 
 

};
const size_t dsp_mode1_ven_TX_size = sizeof(dsp_mode1_ven_TX) / sizeof(reg_config_t);

const reg_config_t dsp_mode1_ven_RX[] =
    {
	{0	 ,0x0028},	  // 2A0,	 RECEIVE_FUNC_REG  : OldTDRC+SPK_HPF+EQ  
	{1	 ,0x0000},	  // 2A1,	 RECEIVE_FUNC_MODE1,  no mapping									 
	{2	 ,0x0001},	  // 2A2,	 SYS_RCV_SAMPLINGFREQ_SIG,	no mapping								 
	{3	 ,0x0001},	  // 2A3,	 SYS_RCV_SAMPLINGFREQ_PROC,  no mapping 							 
	{4	 ,0x000A},	  // 2A4,	 SYS_RCV_FRAME_SZ,	no mapping										 
	{5	 ,0x0000},	  // 2A5,	 SYS_RCV_DELAY_OPT,  no mapping 									 
	{6	 ,0x0000},	  // 2A6,	 RCV_DBG_FUNC_REG,	no mapping										 
	{7	 ,0x00F0},	  // 2A7,	  RCV_NXF,	no mapping												 
	{8	 ,0x0200},	  // 2A8,	 RCV_FRAME_LENGTH,	no mapping										 
	{9	 ,0x0002},	  // 2A9,	 NUM_LINEIN_CHN 												   
	{10  ,0x0800},	  // 2AA,	 LIN_PGA_GAIN,	no mapping											 
	{11  ,0x7B02},	  // 2AB,	SPK_A_HP															 
	{12  ,0x4000},	  // 2AC,	SPK_B_PE															 
	{13  ,0x5000},	  // 2AD,	RCV_THR_PITCH_DET0													 
	{14  ,0x4000},	  // 2AE,	RCV_THR_PITCH_DET1													 
	{15  ,0x3400},	  // 2AF,	RCV_THR_PITCH_DET2													 
	{16  ,0x0008},	  // 2B0,	RCV_PITCH_BFR_LEN,	no mapping										 
	{17  ,0x0003},	  // 2B1,	RCV_SBD_PITCH_DET,	no mapping										 
	{18  ,0x0000},	  // 2B2,	 RCV_PP_RESERV_0													 
	{19  ,0x0050},	  // 2B3,	SPK_N1_SN_EST,	in ms												 
	{20  ,0x0010},	  // 2B4,	SPK_N2_SN_EST														 
	{21  ,0x000F},	  // 2B5,	RCV_NS_level_Control												 
	{22  ,0xF800},	  // 2B6,	SPK_THR_SN_EST														 
	{23  ,0x7E00},	  // 2B7,	RCV_LAMBDA_PFLT 													 
	{24  ,0x000F},	  // 2B8,	 RCV_MIN_G_CTRL_MAXG,  no mapping									 
	{25  ,0x000F},	  // 2B9,	 RCV_MIN_G_CTRL_MING,  no mapping									 
	{26  ,0x0020},	  // 2BA,	 RCV_MIN_G_CTRL_LRUP,  no mapping									 
	{27  ,0x0020},	  // 2BB,	 RCV_MIN_G_CTRL_LRDN,  no mapping									 
	{28  ,0x0200},	  // 2BC,	 RCV_DELTA_THR_SN_EST												 
	{29  ,0x0002},	  // 2BD,	 RCV_EXTRA_NS_L 													 
	{30  ,0x0800},	  // 2BE,	 RCV_EXTRA_NS_A 													 
	{31  ,0x0010},	  // 2BF,	 RCV_K_PEPPER														 
	{32  ,0x0400},	  // 2C0,	 RCV_A_PEPPER														 
	{33  ,0x0010},	  // 2C1,	 RCV_SN_C_F 														 
	{34  ,0x0800},	  // 2C2,	 RCV_A_POST_FLT 													 
	{35  ,0x0000},	  // 2C3,	 FENS_RESERV_0														 
	{36  ,0x0000},	  // 2C4,	 FENS_RESERV_1														 
	{37  ,0x6666},	  // 2C5,	FQ_EQUAL_GAIN_RCV0													 
	{38  ,0x6666},	  // 2C6,	FQ_EQUAL_GAIN_RCV1													 
	{39  ,0x6666},	  // 2C7,	FQ_EQUAL_GAIN_RCV2													 
	{40  ,0x6666},	  // 2C8,	FQ_EQUAL_GAIN_RCV3													 
	{41  ,0x6666},	  // 2C9,	FQ_EQUAL_GAIN_RCV4													 
	{42  ,0x6666},	  // 2CA,	FQ_EQUAL_GAIN_RCV5													 
	{43  ,0x6666},	  // 2CB,	 FQ_EQUAL_GAIN_RCV6 												 
	{44  ,0x6666},	  // 2CC,	 FQ_EQUAL_GAIN_RCV7 												 
	{45  ,0x0000},	  // 2CD,	 FQ_EQUAL_GAIN_RCV8 												 
	{46  ,0x0000},	  // 2CE,	 FQ_EQUAL_GAIN_RCV9 												 
	{47  ,0x0000},	  // 2CF,	 FQ_EQUAL_GAIN_RCV10												 
	{48  ,0x0000},	  // 2D0,	 FQ_EQUAL_GAIN_RCV11												 
	{49  ,0x0000},	  // 2D1,	 FQ_EQUAL_GAIN_RCV12												 
	{50  ,0x0000},	  // 2D2,	 FQ_EQUAL_GAIN_RCV13												 
	{51  ,0x0000},	  // 2D3,	 FQ_EQUAL_GAIN_RCV14												 
	{52  ,0x0000},	  // 2D4,	 FQ_EQUAL_GAIN_RCV15												 
	{53  ,0x0000},	  // 2D5,	 FQ_EQUAL_GAIN_RCV16												 
	{54  ,0x0000},	  // 2D6,	 FQ_EQUAL_GAIN_RCV17												 
	{55  ,0x0000},	  // 2D7,	 FQ_EQUAL_GAIN_RCV18												 
	{56  ,0x0000},	  // 2D8,	 FQ_EQUAL_GAIN_RCV19												 
	{57  ,0x0000},	  // 2D9,	 FQ_EQUAL_GAIN_RCV20												 
	{58  ,0x0000},	  // 2DA,	 FQ_EQUAL_GAIN_RCV21												 
	{59  ,0x0000},	  // 2DB,	 FQ_EQUAL_GAIN_RCV22												 
	{60  ,0x0000},	  // 2DC,	 FQ_EQUAL_GAIN_RCV23												 
	{61  ,0x0000},	  // 2DD,	 FQ_EQUAL_GAIN_RCV_RESERV0											 
	{62  ,0x0012},	  // 2DE,	SPK_FD_DRC_BAND_MARGIN_0											 
	{63  ,0x0040},	  // 2DF,	SPK_FD_DRC_BAND_MARGIN_1											 
	{64  ,0x0080},	  // 2E0,	SPK_FD_DRC_BAND_MARGIN_2											 
	{65  ,0x00EF},	  // 2E1,	SPK_FD_DRC_BAND_MARGIN_3											 
	{66  ,0x0006},	  // 2E2,	SPK_FD_DRC_BLOCK_EXP												 
	{67  ,0x4000},	  // 2E3,	SPK_FD_DRC_THRD_2_0 												 
	{68  ,0x4000},	  // 2E4,	SPK_FD_DRC_THRD_2_1 												 
	{69  ,0x4000},	  // 2E5,	SPK_FD_DRC_THRD_2_2 												 
	{70  ,0x4000},	  // 2E6,	SPK_FD_DRC_THRD_2_3 												 
	{71  ,0x6400},	  // 2E7,	SPK_FD_DRC_THRD_3_0 												 
	{72  ,0x6400},	  // 2E8,	SPK_FD_DRC_THRD_3_1 												 
	{73  ,0x6400},	  // 2E9,	SPK_FD_DRC_THRD_3_2 												 
	{74  ,0x6400},	  // 2EA,	SPK_FD_DRC_THRD_3_3 												 
	{75  ,0x65AC},	  // 2EB,	SPK_FD_DRC_SLANT_0_0												 
	{76  ,0x65AC},	  // 2EC,	SPK_FD_DRC_SLANT_0_1												 
	{77  ,0x65AC},	  // 2ED,	SPK_FD_DRC_SLANT_0_2												 
	{78  ,0x65AC},	  // 2EE,	SPK_FD_DRC_SLANT_0_3												 
	{79  ,0x65AC},	  // 2EF,	SPK_FD_DRC_SLANT_1_0												 
	{80  ,0x65AC},	  // 2F0,	SPK_FD_DRC_SLANT_1_1												 
	{81  ,0x65AC},	  // 2F1,	SPK_FD_DRC_SLANT_1_2												 
	{82  ,0x65AC},	  // 2F2,	SPK_FD_DRC_SLANT_1_3												 
	{83  ,0x0000},	  // 2F3,	 SPK_FD_DRC_RESERV0 												 
	{84  ,0x0001},	  // 2F4,	SPKOUT_HPF_FILTER_INDEX 											 
	{85  ,0x0000},	  // 2F5,	SPK_TD_DRC_THRD_0													 
	{86  ,0x0000},	  // 2F6,	SPK_TD_DRC_THRD_1													 
	{87  ,0x6000},	  // 2F7,	SPK_TD_DRC_THRD_2													 
	{88  ,0x7000},	  // 2F8,	SPK_TD_DRC_THRD_3													 
	{89  ,0x5800},	  // 2F9,	SPK_TD_DRC_SLANT_0													 
	{90  ,0x7800},	  // 2FA,	SPK_TD_DRC_SLANT_1													 
	{91  ,0x0400},	  // 2FB,	SPK_TD_DRC_ALPHA_UP 												 
	{92  ,0x7C00},	  // 2FC,	SPK_TD_DRC_ALPHA_DWN												 
	{93  ,0x0000},	  // 2FD,	SPK_TD_DRC_HMNC_FLAG												 
	{94  ,0x199A},	  // 2FE,	SPK_TD_DRC_HMNC_GAIN												 
	{95  ,0x0001},	  // 2FF,	SPK_TD_DRC_SMT_FLAG 												 
	{96  ,0x1C00},	  // 300,	SPK_TD_DRC_SMT_W													 
	{97  ,0x0000},	  // 301,	SPK_TD_DRC_RESERV0													
	{98  ,0x5300},	  // 302,	SPK_DB_DROP,  Reserved												
	{99  ,0x0044},	  // 303,	SPK_DB_DECAY, Reserved												
	{100 ,0x7EC0},	  // 304,	SPK_ALPHA,		 Reserved											 
	{101 ,0x2000},	  // 305,	SPK_DRC_POSTGAIN													 
	{102 ,0x0100},	  // 306,	SPK_VOLUME															 
	{103 ,0x0000},	  // 307,	SPK_MAXLEVEL_CNG, Reserved											 
	{104 ,0x3000},	  // 308,	BWE_UV_TH															 
	{105 ,0x3000},	  // 309,	BWE_UV_TH2															 
	{106 ,0x1800},	  // 30A,	BWE_UV_TH3															 
	{107 ,0x1000},	  // 30B,	BWE_V_TH															 
	{108 ,0x04CD},	  // 30C,	BWE_GAIN1_V_TH1 													 
	{109 ,0x0F33},	  // 30D,	BWE_GAIN1_V_TH2 													 
	{110 ,0x7333},	  // 30E,	BWE_UV_EQ															 
	{111 ,0x199A},	  // 30F,	BWE_V_EQ															 
	{112 ,0x7333},	  // 310,	BWE_TONE_TH 														 
	{113 ,0x0004},	  // 311,	BWE_UV_HOLD_T														 
	{114 ,0x6CCD},	  // 312,	BWE_GAIN2_ALPHA 													 
	{115 ,0x799A},	  // 313,	BWE_GAIN3_ALPHA 													 
	{116 ,0x001E},	  // 314,	BWE_CUTOFF															 
	{117 ,0x3000},	  // 315,	BWE_GAINFILL														 
	{118 ,0x3200},	  // 316,	BWE_MAXTH_TONE														 
	{119 ,0x2000},	  // 317,	BWE_EQ_0															 
	{120 ,0x2000},	  // 318,	BWE_EQ_1															 
	{121 ,0x2000},	  // 319,	BWE_EQ_2															 
	{122 ,0x2000},	  // 31A,	BWE_EQ_3															 
	{123 ,0x2000},	  // 31B,	BWE_EQ_4															 
	{124 ,0x2000},	  // 31C,	BWE_EQ_5															 
	{125 ,0x2000},	  // 31D,	BWE_EQ_6															 
	{126 ,0x0000},	  // 31E,	BWE_RESERV_0														
	{127 ,0x0000},	  // 31F,	BWE_RESERV_1														
	{128 ,0x0000},	  // 320,	SPK_DRC_QUIET_TH,  old DRC actived								  
	{129 ,0x0000},	  // 321,	SPK_DRC_DECAY_TH													
	{130 ,0x1400},	  // 322,	SPK_DRC_TH1 														
	{131 ,0x1800},	  // 323,	SPK_DRC_TH2 														
	{132 ,0x6000},	  // 324,	SPK_DRC_SLOP1														
	{133 ,0x7800},	  // 325,	SPK_DRC_SLOP2														
	{134 ,0x7000},	  // 326,	SPK_DRC_ALPHA_UP													
	{135 ,0x7EB8},	  // 327,	SPK_DRC_ALPHA_DOWN													
	{136 ,0x0000},	  // 328,	SPK_HMNC_BOOST_GAIN,  old DRC actived							  
	{137 ,0x0000},	  // 329,	RCV_RESERV_0														
	{138 ,0x0000},	  // 32A,	RCV_RESERV_1														
	{139 ,0x0000},	  // 32B,	RCV_RESERV_2														
	{140 ,0xFFFF},	  // 32C,	RCV_RESERV_3														
	{141 ,0xFFFF},	  // 32D,	RCV_RESERV_4														
	{142 ,0x0000},	  // 32E,	RCV_RESERV_5														
	{143 ,0x0103},	  // 32F,	VER_INFO


};

const size_t dsp_mode1_ven_RX_size = sizeof(dsp_mode1_ven_RX) / sizeof(reg_config_t);
#endif
